| Loihi: A Neuromorphic Manycore Processor with On-Chip Learning |
197 |
| Serving DNNs in Real Time at Datacenter Scale with Project Brainwave |
19 |
| Motivation for and Evaluation of the First Tensor Processing Unit |
15 |
| A New Golden Age in Computer Architecture: Empowering the Machine-Learning Revolution |
10 |
| Volta: Performance and Programmability |
10 |
| Walking through the Energy-Error Pareto Frontier of Approximate Multipliers |
8 |
| DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture |
8 |
| Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning |
7 |
| A Microarchitecture for a Superconducting Quantum Processor |
6 |
| Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain |
5 |
| Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration |
5 |
| Toward Dynamic Precision Scaling |
4 |
| Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration |
4 |
| The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips |
4 |
| Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures |
4 |
| Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing |
3 |
| Cascade Lake: Next Generation Intel Xeon Scalable Processor |
3 |
| Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing |
3 |
| Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation |
3 |
| Monolithic 3-D Integration |
2 |
| Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration |
2 |
| Motivating Security-Aware Energy Management |
2 |
| Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks |
2 |
| ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays |
2 |
| Temporal Approximate Function Memoization |
2 |
| SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning |
2 |
| Hardware-Assisted Security in Electronic Control Units Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls |
2 |
| The Queuing-First Approach for Tail Management of Interactive Services |
2 |
| DEEPTOOLS: Compiler and Execution Runtime Extensions for RAPiD AI Accelerator |
2 |
| A Communication-Centric Approach for Designing Flexible DNN Accelerators |
2 |
| Samsung M3 Processor |
2 |
| On the Spectre and Meltdown Processor Security Vulnerabilities |
2 |
| Two Billion Devices and Counting An Industry Perspective on the State of Mobile Computer Architecture |
2 |
| Domain-Specific Approximation for Object Detection |
2 |
| Emerging ADAS Thermal Reliability Needs and Solutions |
1 |
| Die Stacking Is Happening |
1 |
| High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V |
1 |
| The Hardware Security Behind Azure Sphere |
1 |
| Will Carbon Nanotube Memory Replace DRAM? |
1 |
| Accelerators and Coherence: An SoC Perspective |
1 |
| Galapagos: A Full Stack Approach to FPGA Integration in the Cloud |
1 |
| CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM |
1 |
| Image Recognition Accelerator Design Using In-Memory Processing |
1 |
| Write Deduplication and Hash Mode Encryption for Secure Nonvolatile Main Memory |
1 |
| Performance Assessment of Emerging Memories Through FPGA Emulation |
1 |
| Smart Network Interfaces for Advanced Automotive Applications |
1 |
| Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management |
1 |
| Language Support for Memory Persistency |
1 |
| Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach |
1 |
| Nonblocking DRAM Refresh |
1 |
