| Throughput/area optimised pipelined architecture for elliptic curve crypto processor |
5 |
| VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors |
5 |
| Comparative analysis of network-on-chip simulation tools |
4 |
| Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices |
3 |
| Sign detector for the extended four-moduli set {2(n)-2(n)+2(2n)+2(n+k)} |
3 |
| SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit |
3 |
| HASTI: hardware-assisted functional testing of embedded processors in idle times |
2 |
| HEALERS: a heterogeneous energy-aware low-overhead real-time scheduler |
2 |
| Role of circuit representation in evolutionary design of energy-efficient approximate circuits |
2 |
| Fluid-level synthesis unifying reliability, contamination avoidance, and capacity-wastage-aware washing for droplet-based microfluidic biochips |
2 |
| Kernel and layer vulnerability factor to evaluate object detection reliability in GPUs |
2 |
| Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs |
2 |
| Static test compaction procedure for large pools of multicycle functional broadside tests |
2 |
| ON-OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs |
2 |
| P-EdgeCoolingMode: an agent-based performance aware thermal management unit for DVFS enabled heterogeneous MPSoCs |
2 |
| Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs |
2 |
| P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices |
2 |
| Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry |
1 |
| Efficient spiking neural network training and inference with reduced precision memory and computing |
1 |
| Approach of genetic algorithm for power-aware testing of 3D IC |
1 |
| High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA |
1 |
| Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application |
1 |
| Reducing bypass-based network-on-chip latency using priority mechanism |
1 |
| Test data compression using hierarchical block merging technique |
1 |
| Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms |
1 |
| Locality-protected cache allocation scheme with low overhead on GPUs |
1 |
| MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis |
1 |
| Design of an extended 2D mesh network-on-chip and development of A fault-tolerant routing method |
1 |
| Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes |
1 |
| KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC |
1 |
| Exploiting memory allocations in clusterised many-core architectures |
1 |
| DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems |
1 |
| Accuracy enhancement of equal segment based approximate adders |
1 |
| Partitioned security processor architecture on FPGA platform |
1 |
| 65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography |
1 |
| Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics |
1 |
| Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures |
1 |
| CUDA memory optimisation strategies for motion estimation |
1 |
| Dynamic scheduling of tasks for multi-core real-time systems based on optimum energy and throughput |
1 |
| Efficient digital implementation of a multi-precision square-root algorithm |
1 |
| Performance and energy aware robust specification of control execution patterns under dropped samples |
1 |
| Resilient training of neural network classifiers with approximate computing techniques for hardware-optimised implementations |
1 |
| Energy efficient VLSI architecture of real-valued serial pipelined FFT |
0 |
| Soft-error reliable architecture for future microprocessors |
0 |
| Removing constant-induced errors in stochastic circuits |
0 |
| RASSS: a hijack-resistant confidential information management scheme for distributed systems |
0 |
| Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors |
0 |
| Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder |
0 |
| Yield modelling and analysis of bundled data and ring-oscillator based designs |
0 |
| Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ |
0 |
