| FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks |
13 |
| [DL] A Survey of FPGA-based Neural Network Inference Accelerators |
10 |
| NEURAGHE: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs |
5 |
| An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse |
5 |
| Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA |
4 |
| COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures |
4 |
| FeatherNet: An Accelerated Convolutional Neural Network Design for Resource-constrained FPGAs |
4 |
| Recent Attacks and Defenses on FPGA-based Systems |
3 |
| RIPL: A Parallel Image Processing Language for FPGAs |
3 |
| General-Purpose Computing with Soft GPUs on FPGAs |
3 |
| Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA |
3 |
| High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression |
3 |
| Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs |
3 |
| Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve |
2 |
| You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference |
2 |
| In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms |
2 |
| Distributed Inference over Decision Tree Ensembles on Clusters of FPGAs |
2 |
| A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows |
2 |
| Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud |
2 |
| Framework for Rapid Performance Estimation of Embedded Soft Core Processors |
1 |
| Automated Synthesis of Streaming Transfer Level Hardware Designs |
1 |
| Lightening the Load with Highly Accurate Storage-and Energy-Efficient LightNNs |
1 |
| KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs |
1 |
| Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems |
1 |
| High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors |
1 |
| Unrolling Ternary Neural Networks |
1 |
| Automata Processing in Reconfigurable Architectures: In-the-Cloud Deployment, Cross-Platform Evaluation, and Fast Symbol-Only Reconfiguration |
1 |
| Fast Adjustable NPN Classification Using Generalized Symmetries |
1 |
| Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform |
1 |
| FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL |
1 |
| Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays |
0 |
| PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization |
0 |
| A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and Compensation |
0 |
| Exact and Practical Modulo Scheduling for High-Level Synthesis |
0 |
| FRoC 2.0: Automatic BRAM and Logic Testing to Enable Dynamic Voltage Scaling for FPGA Applications |
0 |
| GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms |
0 |
| The FPOA, a Medium-grained Reconfigurable Architecture for High-level Synthesis |
0 |
| An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures |
0 |
| Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs |
0 |
| Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP) |
0 |
| FlexSaaS: A Reconfigurable Accelerator for Web Search Selection |
0 |
| ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs |
0 |
| Wotan: Evaluating FPGA Architecture Routability without Benchmarks |
0 |
| Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs |
0 |
| Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing |
0 |
| Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks |
0 |
| A Protection and Pay-per-use Licensing Scheme for On-cloud FPGA Circuit IPs |
0 |
