Ieee Transactions On Very Large Scale Integration (vlsi) Systems投稿须知

期刊简介

《Ieee Transactions On Very Large Scale Integration (vlsi) Systems》是由Institute of Electrical and Electronics Engineers Inc.出版社于1993年创办的英文国际期刊（ISSN: 1063-8210，E-ISSN: 1557-9999），该期刊长期致力于计算机：硬件领域的创新研究，主要研究方向为工程技术-工程：电子与电气。作为SCIE收录期刊（JCR分区 Q2，中科院 2区），本刊采用OA未开放获取模式（OA占比0%），以发表计算机：硬件领域等方向的原创性研究为核心（研究类文章占比99.59%%）。凭借严格的同行评审与高效编辑流程，期刊年载文量精选控制在241篇，确保学术质量与前沿性。成果覆盖Web of Science、Scopus等国际权威数据库，为学者提供推动工程技术领域高水平交流平台。

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Ieee Transactions On Very Large Scale Integration (vlsi) Systems审稿周期约为一般,3-6周。该刊近年未被列入国际预警名单，年发文量约241篇，录用竞争适中，主题需确保紧密契合工程技术前沿。投稿策略提示：避开学术会议旺季投稿以缩短周期，语言建议专业润色提升可读性。

工程技术 大类学科
English 出版语言
否是否预警
SCIE 期刊收录
241 发文量

中科院分区

中科院 SCI 期刊分区 2023年12月升级版

Top期刊	综述期刊	大类学科	小类学科
否	否	工程技术 2区	COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：电子与电气 2区 3区

中科院 SCI 期刊分区 2022年12月升级版

Top期刊	综述期刊	大类学科	小类学科
否	否	工程技术 2区	COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机：硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程：电子与电气 3区 3区

JCR分区

按JIF指标学科分区	收录子集	分区	排名	百分位
学科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE	SCIE	Q2	23 / 59	61.9%
学科：ENGINEERING, ELECTRICAL & ELECTRONIC	SCIE	Q2	151 / 352	57.2%

按JCI指标学科分区	收录子集	分区	排名	百分位
学科：COMPUTER SCIENCE, HARDWARE & ARCHITECTURE	SCIE	Q2	26 / 59	56.78%
学科：ENGINEERING, ELECTRICAL & ELECTRONIC	SCIE	Q2	149 / 354	58.05%

CiteScore

SJR

SNIP

CiteScore 排名

CiteScore：6.4

SJR：0.937

SNIP：1.516

学科类别	分区	排名	百分位
大类：Engineering 小类：Electrical and Electronic Engineering	Q1	195 / 797	75%
大类：Engineering 小类：Hardware and Architecture	Q2	51 / 177	71%
大类：Engineering 小类：Software	Q2	124 / 407	69%

期刊发文

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
Author: Bai, Fujun; Wang, Song; Jia, Xuerong; Guo, Yixin; Yu, Bing; Wang, Hang; Lai, Cong; Ren, Qiwei; Sun, Hongbin

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 128-141. DOI: 10.1109/TVLSI.2022.3219437
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-mu W Embedded RRAM and Reconfigurable Strong PUF
Author: Ren, Qirui; Huo, Qiang; Chen, Zhisheng; Gao, Qi; Wang, Yiming; Yang, Yiming; Wu, Hao; Fu, Xiangqu; Xu, Xiaoxin; Luo, Qing; Gao, Jianfeng; Chen, Chengying; Zhao, Xiaojin; Lei, Dengyun; Wang, Xinghua; Zhang, Feng; Chen, Yong; Mak, Pui-In

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 243-252. DOI: 10.1109/TVLSI.2022.3222522
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique
Author: Wang, Yujia; Zhang, Jincheng; Chen, Yong; Ren, Junyan; Ma, Shunli

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 233-242. DOI: 10.1109/TVLSI.2022.3225967
Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method
Author: Wang, Jun; Luo, Yuhuan; Guo, Wenting; Wu, Feng; Chu, Xiuqin

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 210-218. DOI: 10.1109/TVLSI.2022.3225533
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors
Author: Tan, Hongbing; Tong, Gan; Huang, Libo; Xiao, Liquan; Xiao, Nong

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 2, pp. 253-266. DOI: 10.1109/TVLSI.2022.3226185
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs
Author: Qiu, Lei; Meng, Tianyi; Yao, Bingbing; Du, Zihao; Yuan, Xiaohua

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 152-156. DOI: 10.1109/TVLSI.2022.3224237
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks
Author: Li, Hongyan; Lu, Hang; Wang, Haoxuan; Deng, Shengji; Li, Xiaowei

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 90-103. DOI: 10.1109/TVLSI.2022.3221732
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders
Author: Gao, Zhen; Shi, Jinchang; Liu, Qiang; Ullah, Anees; Reviriego, Pedro

Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2023; Vol. 31, Issue 1, pp. 142-146. DOI: 10.1109/TVLSI.2022.3224137

Ieee Transactions On Very Large Scale Integration (vlsi) Systems

超大规模集成 (vlsi) 系统上的 Ieee 事务

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中科院分区

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