| Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach |
58 |
| Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA |
27 |
| Computing in Memory With Spin-Transfer Torque Magnetic RAM |
22 |
| A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection |
19 |
| Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach |
13 |
| Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates |
13 |
| Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder |
12 |
| Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test |
12 |
| Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM |
12 |
| Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application |
12 |
| High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic |
12 |
| An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks |
11 |
| Three-Dimensional NAND Flash for Vector-Matrix Multiplication |
11 |
| A Simple Floating MOS-Memristor for High-Frequency Applications |
10 |
| A Global Bayesian Optimization Algorithm and Its Application to Integrated System Design |
10 |
| Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits |
9 |
| Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications |
9 |
| TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier |
9 |
| Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits |
9 |
| 8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing |
9 |
| Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers |
9 |
| ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration |
8 |
| A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications |
8 |
| Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications |
8 |
| A Simple Yet Efficient Accuracy-Configurable Adder Design |
7 |
| A Reliable Strong PUF Based on Switched-Capacitor Circuit |
7 |
| PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration |
7 |
| Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors |
7 |
| TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches |
7 |
| Neuromorphic Vision Hybrid RRAM-CMOS Architecture |
7 |
| A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs |
7 |
| Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning |
7 |
| Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review |
7 |
| A 0.9-V 33.7-ppm/degrees C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT |
7 |
| Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms |
7 |
| Inkjet-Printed EGFET-Based Physical Unclonable Function-Design, Evaluation, and Fabrication |
7 |
| An RF-DC Converter IC With On-Chip Adaptive Impedance Matching and 307-mu W Peak Output Power for Health Monitoring Applications |
6 |
| Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy |
6 |
| A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G |
6 |
| High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure |
6 |
| 28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication |
6 |
| A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar |
6 |
| A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing |
6 |
| High-Density SOT-MRAM Based on Shared Bitline Structure |
6 |
| High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture |
6 |
| A New Fast-Response Current-Mode Buck Converter With Improved I-2-Controlled Techniques |
6 |
| Accelerating Convolutional Neural Network With FFT on Embedded Hardware |
6 |
| Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators |
6 |
| Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture |
5 |
| An Ultralow Power Subthreshold CMOS Voltage Reference Without Requiring Resistors or BJTs |
5 |
