| Computer vision algorithms and hardware implementations: A survey |
17 |
| Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED |
10 |
| Integrated circuit packaging review with an emphasis on 3D packaging |
9 |
| An energy and area efficient 4:2 compressor based on FinFETs |
7 |
| ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler |
7 |
| Design of UWB low noise amplifier using noise-canceling and current-reused techniques |
6 |
| A SPAD-based random number generator pixel based on the arrival time of photons |
6 |
| An accurate classifier based on adaptive neuro-fuzzy and features selection techniques for fault classification in analog circuits |
6 |
| A low-power dynamic comparator for low-offset applications |
6 |
| Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view |
6 |
| Toward automated reasoning for analog IC design by symbolic computation - A survey |
5 |
| Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited) |
5 |
| Ultra-low latency communication channels for FPGA-based HPC cluster |
5 |
| A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates |
5 |
| Offline Testing of Reversible Logic Circuits: An Analysis |
4 |
| A new low-power dynamic circuit for wide fan-in gates |
4 |
| A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer |
4 |
| Runtime hardware Trojan monitors through modeling burst mode communication using formal verification |
4 |
| Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications |
4 |
| A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power |
4 |
| A Fully RNS based ECC Processor |
3 |
| In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC) |
3 |
| Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding |
3 |
| A highly linear current-starved VCO based on a linearized current control mechanism |
3 |
| Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs |
3 |
| Look-ahead mapping of Boolean functions in memristive crossbar array |
3 |
| Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication |
3 |
| A novel design methodology for the mixed-domain optimization of a MEMS accelerometer |
3 |
| Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources |
3 |
| A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier |
3 |
| Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation |
3 |
| A low-voltage low-power capacitive-feedback voltage controlled oscillator |
3 |
| Strategy of logic synthesis using MTBDD dedicated to FPGA |
3 |
| Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems |
3 |
| Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design |
2 |
| Realizations of simple fractional-order capacitor emulators with electronically-tunable capacitance |
2 |
| Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators |
2 |
| Rapid and coding-efficient SPIHT algorithm for wavelet-based ECG data compression |
2 |
| An improved communication scheme for non-HOL-blocking wireless NoC |
2 |
| A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits |
2 |
| An efficient hardware architecture for detection of vowel-like regions in speech signal |
2 |
| Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons |
2 |
| Super class AB-AB bulk-driven folded cascode OTA |
2 |
| A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier |
2 |
| Architectural exploration of perpendicular Nano Magnetic Logic based circuits |
2 |
| 3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications |
2 |
| Scalable lumped models of integrated transformers for galvanically isolated power transfer systems |
2 |
| Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator |
2 |
| Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology |
2 |
| Verilntel2C: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration |
2 |
