Ieee Journal Of Solid-state Circuits

Ieee Journal Of Solid-state Circuits

IEEE固态电路杂志

  • 1区 中科院分区
  • Q1 JCR分区

期刊简介

《Ieee Journal Of Solid-state Circuits》是由Institute of Electrical and Electronics Engineers Inc.出版社于1966年创办的英文国际期刊(ISSN: 0018-9200,E-ISSN: 1558-173X),该期刊长期致力于工程:电子与电气领域的创新研究,主要研究方向为工程技术-工程:电子与电气。作为SCIE收录期刊(JCR分区 Q1,中科院 1区),本刊采用OA未开放获取模式(OA占比0%),以发表工程:电子与电气领域等方向的原创性研究为核心(研究类文章占比100.00%%)。凭借严格的同行评审与高效编辑流程,期刊年载文量精选控制在304篇,确保学术质量与前沿性。成果覆盖Web of Science、Scopus等国际权威数据库,为学者提供推动工程技术领域高水平交流平台。

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投稿提示

Ieee Journal Of Solid-state Circuits审稿周期约为 一般,3-6周 。该刊近年未被列入国际预警名单,年发文量约304篇,录用竞争适中,主题需确保紧密契合工程技术前沿。投稿策略提示:避开学术会议旺季投稿以缩短周期,语言建议专业润色提升可读性。

  • 工程技术 大类学科
  • English 出版语言
  • 是否预警
  • SCIE 期刊收录
  • 304 发文量

中科院分区

中科院 SCI 期刊分区 2023年12月升级版

Top期刊 综述期刊 大类学科 小类学科
工程技术
1区
ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
1区

中科院 SCI 期刊分区 2022年12月升级版

Top期刊 综述期刊 大类学科 小类学科
工程技术
1区
ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
1区

JCR分区

按JIF指标学科分区 收录子集 分区 排名 百分位
学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q1 74 / 352

79.1%

按JCI指标学科分区 收录子集 分区 排名 百分位
学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q1 66 / 354

81.5%

CiteScore

CiteScore SJR SNIP CiteScore 排名
CiteScore:11 SJR:2.876 SNIP:2.612
学科类别 分区 排名 百分位
大类:Engineering 小类:Electrical and Electronic Engineering Q1 78 / 797

90%

期刊发文

  • Configurable Hybrid Energy Synchronous Extraction Interface With Serial Stack Resonance for Multi-Source Energy Harvesting

    Author: Wang, Xiudeng; Xia, Yinshui; Zhu, Zhangming; Shi, Ge; Xia, Huakang; Ye, Yidie; Chen, Zhidong; Qian, Libo; Liu, Lianxi

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 451-461. DOI: 10.1109/JSSC.2022.3182118

  • A D-Band Joint Radar-Communication CMOS Transceiver

    Author: Deng, Wei; Chen, Zipeng; Jia, Haikun; Guan, Pingda; Ma, Taikun; Yan, Angxiao; Sun, Shiyan; Huang, Xiangrong; Chen, Guopei; Ma, Ruichang; Dong, Shengnan; Duan, Luqiang; Wang, Zhihua; Chi, Baoyong

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 411-427. DOI: 10.1109/JSSC.2022.3185160

  • A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction

    Author: Guo, Yuekang; Jin, Jing; Liu, Xiaoming; Zhou, Jianjun

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 474-485. DOI: 10.1109/JSSC.2022.3185501

  • A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P-SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS

    Author: Yu, Jiayang; Chen, Jixin; Zhou, Peigen; Li, Huanbo; Wang, Zuojun; Li, Zekun; Chen, Zhe; Yan, Pinpin; Hou, Debin; Gao, Hao; Hong, Wei

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 332-344. DOI: 10.1109/JSSC.2022.3192043

  • A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer

    Author: Yang, Bingzheng; Qian, Huizhen Jenny; Wang, Tianyi; Luo, Xun

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 357-370. DOI: 10.1109/JSSC.2022.3191975

  • A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS

    Author: Hu, Chunxiao; Yin, Yun; Li, Tong; Liu, Yangzi; Xiong, Liang; Xu, Hongtao

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 462-473. DOI: 10.1109/JSSC.2022.3192281

  • A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS

    Author: Bose, Sumon Kumar; Basu, Arindam

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 554-568. DOI: 10.1109/JSSC.2022.3194098

  • A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS

    Author: Jia, Haikun; Guan, Pingda; Deng, Wei; Wang, Zhihua; Chi, Baoyong

    Journal: IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2023; Vol. 58, Issue 2, pp. 371-385. DOI: 10.1109/JSSC.2022.3196181