| A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a 2 x 2 Beamformer Flip-Chip Unit Cell |
52 |
| Cryo-CMOS Circuits and Systems for Quantum Computing Applications |
29 |
| A 28-GHz CMOS Direct Conversion Transceiver With Packaged 2 x 4 Antenna Array for 5G Cellular System |
29 |
| A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS |
25 |
| A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array |
24 |
| A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications |
23 |
| An Always-On 3.8 mu J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS |
19 |
| A Wideband Class-AB Power Amplifier With 29-57-GHz AM-PM Compensation in 0.9-V 28-nm Bulk CMOS |
19 |
| A 28-/37-/39-GHz Linear Doherty Power Amplifier in Silicon for 5G Applications |
18 |
| An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator |
18 |
| A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute |
17 |
| UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision |
17 |
| A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio |
16 |
| A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming |
16 |
| BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W |
15 |
| A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure |
15 |
| CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks |
15 |
| A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control |
14 |
| A 25-30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication |
14 |
| DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications |
14 |
| Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators |
13 |
| A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS |
13 |
| Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits |
13 |
| A Nonuniform Sparse 2-D Large-FOV Optical Phased Array With a Low-Power PWM Drive |
13 |
| A 12-Bit 1. 3. and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation |
13 |
| A Near-Zero-Power Wake-Up Receiver Achieving-69-dBm Sensitivity |
12 |
| A 60-GHz 144-Element Phased-Array Transceiver for Backhaul Application |
12 |
| A 192 x 128 Time Correlated SPAD Image Sensor in 40-nm CMOS Technology |
12 |
| A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting |
12 |
| A 28-GHz Flip-Chip Packaged Chireix Transmitter With On-Antenna Outphasing Active Load Modulation |
12 |
| A Miniaturized Single-Transducer Implantable Pressure Sensor With Time-Multiplexed Ultrasonic Data and Power Links |
12 |
| A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS |
12 |
| Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate |
12 |
| Simultaneously Broadband and Back-Off Efficient mm-Wave PAs: A Multi-Port Network Synthesis Approach |
12 |
| Fully Immersible Subcortical Neural Probes With Modular Architecture and a Delta-Sigma ADC Integrated Under Each Electrode for Parallel Readout of 144 Recording Sites |
12 |
| A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training |
12 |
| NURIP: Neural Interface Processor for Brain-State Classification and Programmable-Waveform Neurostimulation |
12 |
| A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique |
12 |
| A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control |
12 |
| Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm |
12 |
| A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging |
11 |
| An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS |
11 |
| Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator |
11 |
| Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4x Frequency Edge Combiner |
11 |
| A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance |
11 |
| High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure |
11 |
| A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 x 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC |
11 |
| An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique |
11 |
| MISIMO: A Multi-Input Single-Inductor Multi-Output Energy Harvesting Platform in 28-nm FDSOI for Powering Net-Zero-Energy Systems |
11 |
| A 0.18-V 382-mu W Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS |
11 |
