| Energy efficient wearable sensor node for IoT-based fall detection systems |
24 |
| A FPGA based implementation of Sobel edge detection |
13 |
| High speed FPGA-based chaotic oscillator design |
10 |
| A novel approach to improve multimedia security utilizing 3D mixed chaotic map |
10 |
| Rent's rule and extensibility in quantum computing |
10 |
| FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator |
9 |
| Processing data where it makes sense: Enabling in-memory computation |
8 |
| A survey of Open-Source UAV flight controllers and flight simulators |
7 |
| Embedding Recurrent Neural Networks in Wearable Systems for Real-Time Fall Detection |
7 |
| A novel rising Edge Triggered Resettable D flip-flop using five input majority gate |
7 |
| The electronic interface for quantum processors |
7 |
| An optimal design of QCA based 2(n):1/1:2(n) multiplexer/demultiplexer and its efficient digital logic realization |
7 |
| Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features |
6 |
| A system on chip for melanoma detection using FPGA-based SVM classifier |
6 |
| Crosstalk analysis of coupled MLGNR interconnects with different types of repeater insertion |
5 |
| Adaptive-Classification CLOCK: Page replacement policy based on read/write access pattern for hybrid DRAM and PCM main memory |
5 |
| S-box-based random number generation for stochastic computing |
5 |
| Efficient separable convolution using field programmable gate arrays |
5 |
| Constant-time hardware computation of elliptic curve scalar multiplication around the 128 bit security level |
5 |
| Effects of RPL objective functions on the primitive characteristics of mobile and static IoT infrastructures |
5 |
| A fuzzy Anti-lock braking system (ABS) controller using CMOS circuits |
5 |
| A reliability-aware resource provisioning scheme for real-time industrial applications in a Fog-integrated smart factory |
4 |
| P4-To-VHDL: Automatic generation of high-speed input and output network blocks |
4 |
| Investigation of modified multilevel inverter topology for PV system |
4 |
| Test pattern generation using thermometer code counter in TPC technique for BIST implementation |
4 |
| Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip |
4 |
| A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms |
4 |
| SFN: A new lightweight block cipher |
4 |
| Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology |
4 |
| An efficient design of Quantum-dot Cellular Automata based 5-input majority gate with power analysis |
4 |
| ROLFER: A fully autonomous aerial rescue support system |
4 |
| A scalable and adaptable hardware NoC-based self organizing map |
4 |
| Exploring manycore architectures for next-generation HPC systems through the MANGO approach |
4 |
| Composition of switching lattices for regular and for decomposed functions |
3 |
| Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development |
3 |
| The MegaM@Rt2 ECSEL project: MegaModelling at Runtime - Scalable model-based framework for continuous development and runtime validation of complex systems |
3 |
| Acceleration of brain cancer detection algorithms during surgery procedures using GPUs |
3 |
| A parallel implementation of sequential minimal optimization on FPGA |
3 |
| PowerTap: All-digital power meter modeling for run-time power monitoring |
3 |
| Long-short range communication network leveraging LoRa (TM) and wake-up receiver |
3 |
| Accelerating the evolution of a systolic array-based evolvable hardware system |
3 |
| High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications |
3 |
| The ANTAREX domain specific language for high performance computing |
3 |
| FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems |
3 |
| Autonomous power management in mobile devices using dynamic frequency scaling and reinforcement learning for energy minimization |
3 |
| Architecture and FPGA prototype of cycle stealing DMA array signal processor for ultrasound sector imaging systems |
3 |
| Design and leakage assessment of side channel attack resistant binary edwards Elliptic Curve digital signature algorithm architectures |
3 |
| Near-memory computing: Past, present, and future |
3 |
| Non linearity mitigation and dispersion reduction using Bussgang theorem, modified MSE and improved MLE equalizers |
3 |
| Lightweight chaotic image encryption algorithm for real-time embedded system: Implementation and analysis on 32-bit microcontroller |
3 |
