Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems

Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems

集成电路和系统的计算机辅助设计IEEE Transactions

  • 3区 中科院分区
  • Q2 JCR分区

期刊简介

《Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems》是由Institute of Electrical and Electronics Engineers Inc.出版社于1982年创办的英文国际期刊(ISSN: 0278-0070,E-ISSN: 1937-4151),该期刊长期致力于计算机:硬件领域的创新研究,主要研究方向为工程技术-工程:电子与电气。作为SCI、SCIE收录期刊(JCR分区 Q2,中科院 3区),本刊采用OA未开放获取模式(OA占比%),以发表计算机:硬件领域等方向的原创性研究为核心(研究类文章占比100.00%%)。凭借严格的同行评审与高效编辑流程,期刊年载文量精选控制在385篇,确保学术质量与前沿性。成果覆盖Web of ScienceWeb of Science、Scopus等国际权威数据库,为学者提供推动计算机科学领域高水平交流平台。

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投稿提示

Ieee Transactions On Computer-aided Design Of Integrated Circuits And Systems审稿周期约为一般,3-8周。该刊近年未被列入国际预警名单,年发文量约385篇,录用竞争适中,主题需确保紧密契合计算机科学前沿。投稿策略提示:避开学术会议旺季投稿以缩短周期,语言建议专业润色提升可读性。

  • 计算机科学 大类学科
  • English 出版语言
  • 是否预警
  • SCI、SCIE 期刊收录
  • 385 发文量

中科院分区

《新锐期刊分区表》(2026年3月发布)

Top期刊 综述期刊 大类学科 小类学科
计算机科学
3区
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS 计算机:跨学科应用 ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
3区 3区 3区

期刊分区表(2025年3月升级版)

Top期刊 综述期刊 大类学科 小类学科
计算机科学
3区
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS 计算机:跨学科应用 ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
3区 3区 3区

期刊分区表(2023年12月升级版)

Top期刊 综述期刊 大类学科 小类学科
计算机科学
3区
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS 计算机:跨学科应用 ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
3区 3区 3区

期刊分区表(2022年12月升级版)

Top期刊 综述期刊 大类学科 小类学科
计算机科学
3区
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS 计算机:跨学科应用 ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气
3区 3区 3区

期刊分区表(2021年12月升级版)

Top期刊 综述期刊 大类学科 小类学科
计算机科学
2区
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE 计算机:硬件 ENGINEERING, ELECTRICAL & ELECTRONIC 工程:电子与电气 COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS 计算机:跨学科应用
2区 2区 3区

JCR分区

2025-2026年最新版

按JCI指标学科分区 收录子集 分区 排名 百分位
学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 23 / 60

62.5

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q2 89 / 185

52.2

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 142 / 369

61.7

学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q3 31 / 61

50

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q3 98 / 185

47.3

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 150 / 371

59.7

2024-2025年最新版

按JCI指标学科分区 收录子集 分区 排名 百分位
学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 24 / 60

60.8

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q3 90 / 177

49.4

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 162 / 368

56.1

学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 26 / 60

57.5

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q2 80 / 177

55.08

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 144 / 368

61.01

2023-2024年最新版

按JCI指标学科分区 收录子集 分区 排名 百分位
学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 27 / 59

55.1

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q2 76 / 169

55.3

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 154 / 352

56.4

学科:COMPUTER SCIENCE, HARDWARE & ARCHITECTURE SCIE Q2 28 / 59

53.39

学科:COMPUTER SCIENCE, INTERDISCIPLINARY APPLICATIONS SCIE Q2 82 / 169

51.78

学科:ENGINEERING, ELECTRICAL & ELECTRONIC SCIE Q2 152 / 354

57.2

CiteScore(2026年6月最新版)

CiteScore SJR SNIP CiteScore 排名
CiteScore:7.2 SJR:0.928 SNIP:1.514
学科类别 分区 排名 百分位
大类:Computer Science 小类:Computer Graphics and Computer-Aided Design Q1 25 / 131

81%

大类:Computer Science 小类:Electrical and Electronic Engineering Q1 201 / 1030

80%

大类:Computer Science 小类:Software Q2 131 / 503

74%

期刊发文

  • A Full-Stack Framework for GNN Acceleration via Partition-Compiler-Architecture Co-Desig

    Author: Zhou, Yangjie; Zhang, Zhihui; Lu, Shuwen; Guo, Cong; Leng, Jingwen; Zhang, Feng; Ma, Yufei; Liang, Yun; Guo, Minyi

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2348-2361. DOI: 10.1109/TCAD.2025.3610582

  • Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Contro

    Author: Zhou, Xinbing; Liu, Tianlang; Tang, Tiancheng; Man, Yi; Hao, Peng; Chen, Wei; Liu, Dake

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2418-2431. DOI: 10.1109/TCAD.2025.3611113

  • ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environment

    Author: Zhou, Ao; Yang, Jianlei; Qiao, Tong; Qi, Yingjie; Wei, Xinming; Duan, Cenlin; Zhao, Weisheng; Hu, Chunming

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2334-2347. DOI: 10.1109/TCAD.2025.3617863

  • Registry: Enhancing Vertex Reusability for GCN Inference on Hybrid Stacked Memor

    Author: Zhong, Zhaoyu; Chen, Jiaxian; Dong, Yunhao; Wang, Tianyu; Ma, Chenlin; Mao, Rui; Wang, Yi

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2376-2389. DOI: 10.1109/TCAD.2025.3612868

  • Terafly: A Multinode FPGA-Based Accelerator Design for Efficient Cooperative Inference in LLM

    Author: Zheng, Jianing; Chen, Gang; Huang, Libo; Lou, Xin; Zheng, Wei-Shi

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2446-2459. DOI: 10.1109/TCAD.2025.3616078

  • Safe Reinforcement Learning for NN-Controlled Systems With Neural Barrier Certificate Guidanc

    Author: Zhao, Hanrui; Ren, Mengxin; Liu, Banglong; Qi, Niuniu; Zeng, Xia; Zeng, Zhenbing; Yang, Zhengfeng

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2460-2473. DOI: 10.1109/TCAD.2025.3616856

  • A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerator

    Author: Zhang, Yubo; Ye, Yaoyao

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2123-2135. DOI: 10.1109/TCAD.2025.3593438

  • MUXLeak: Exploiting Multiplexers as a Power Side Channel Against Multitenant FPGA

    Author: Zhang, Xin; Zou, Jiajun; Zhang, Zhi; Shen, Qingni; Gao, Yansong; Cui, Jinhua; Feng, Yusi; Wu, Zhonghai; Abbott, Derek

    Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2280-2293. DOI: 10.1109/TCAD.2025.3611878