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A Full-Stack Framework for GNN Acceleration via Partition-Compiler-Architecture Co-Desig
Author: Zhou, Yangjie; Zhang, Zhihui; Lu, Shuwen; Guo, Cong; Leng, Jingwen; Zhang, Feng; Ma, Yufei; Liang, Yun; Guo, Minyi
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2348-2361. DOI: 10.1109/TCAD.2025.3610582
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Efficient Instruction Fusion for ASIPs: A Low-Cost Approach to Structural Hazard Contro
Author: Zhou, Xinbing; Liu, Tianlang; Tang, Tiancheng; Man, Yi; Hao, Peng; Chen, Wei; Liu, Dake
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2418-2431. DOI: 10.1109/TCAD.2025.3611113
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ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environment
Author: Zhou, Ao; Yang, Jianlei; Qiao, Tong; Qi, Yingjie; Wei, Xinming; Duan, Cenlin; Zhao, Weisheng; Hu, Chunming
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2334-2347. DOI: 10.1109/TCAD.2025.3617863
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Registry: Enhancing Vertex Reusability for GCN Inference on Hybrid Stacked Memor
Author: Zhong, Zhaoyu; Chen, Jiaxian; Dong, Yunhao; Wang, Tianyu; Ma, Chenlin; Mao, Rui; Wang, Yi
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2376-2389. DOI: 10.1109/TCAD.2025.3612868
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Terafly: A Multinode FPGA-Based Accelerator Design for Efficient Cooperative Inference in LLM
Author: Zheng, Jianing; Chen, Gang; Huang, Libo; Lou, Xin; Zheng, Wei-Shi
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2446-2459. DOI: 10.1109/TCAD.2025.3616078
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Safe Reinforcement Learning for NN-Controlled Systems With Neural Barrier Certificate Guidanc
Author: Zhao, Hanrui; Ren, Mengxin; Liu, Banglong; Qi, Niuniu; Zeng, Xia; Zeng, Zhenbing; Yang, Zhengfeng
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2460-2473. DOI: 10.1109/TCAD.2025.3616856
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A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerator
Author: Zhang, Yubo; Ye, Yaoyao
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2123-2135. DOI: 10.1109/TCAD.2025.3593438
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MUXLeak: Exploiting Multiplexers as a Power Side Channel Against Multitenant FPGA
Author: Zhang, Xin; Zou, Jiajun; Zhang, Zhi; Shen, Qingni; Gao, Yansong; Cui, Jinhua; Feng, Yusi; Wu, Zhonghai; Abbott, Derek
Journal: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 2026; Vol. 45, Issue 5, pp. 2280-2293. DOI: 10.1109/TCAD.2025.3611878