| Resource Management for Improving Soft-Error and Lifetime Reliability of Real-Time MPSoCs |
50 |
| Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA |
42 |
| NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning |
34 |
| QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware IoT Lifetime Optimization |
28 |
| Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method |
26 |
| YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration |
23 |
| The Promise and Challenge of Stochastic Computing |
20 |
| An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures |
18 |
| DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters |
17 |
| Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems |
17 |
| MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip |
17 |
| Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks |
17 |
| Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor |
13 |
| An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata |
12 |
| FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices |
12 |
| XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference |
12 |
| Secure Scan and Test Using Obfuscation Throughout Supply Chain |
10 |
| A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit |
10 |
| Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis |
10 |
| Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions |
10 |
| Anti-SAT: Mitigating SAT Attack on Logic Locking |
9 |
| Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF |
9 |
| Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization |
9 |
| Secure Randomized Checkpointing for Digital Microfluidic Biochips |
8 |
| System-on-a-Chip (SoC)-Based Hardware Acceleration for an Online Sequential Extreme Learning Machine (OS-ELM) |
8 |
| GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration |
8 |
| Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication |
8 |
| An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT) |
7 |
| Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips |
7 |
| TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip |
7 |
| Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips |
7 |
| One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic |
7 |
| Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips |
7 |
| Microprocessor Optimizations for the Internet of Things: A Survey |
7 |
| Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips |
7 |
| A Data-Driven Verilog-A ReRAM Model |
6 |
| STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition |
6 |
| Design of Application-Specific Architectures for Networked Labs-on-Chips |
6 |
| Power Grid Electromigration Checking Using Physics-Based Models |
6 |
| Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption |
6 |
| Are We There Yet? A Study on the State of High-Level Synthesis |
6 |
| Automated Dimensioning of Networked Labs-on-Chip |
6 |
| Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation |
6 |
| Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach |
6 |
| From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration |
5 |
| Energy-Aware Design of Stochastic Applications With Statistical Deadline and Reliability Guarantees |
5 |
| HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks |
5 |
| A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar |
5 |
| Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers |
5 |
| Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip |
5 |
