| A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors |
9 |
| Efficient In-Memory Processing Using Spintronics |
7 |
| The Architectural Implications of Cloud Microservices |
6 |
| SimpleSSD: Modeling Solid State Drives for Holistic System Simulation |
5 |
| Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing |
5 |
| PPT-GPU: Scalable GPU Performance Modeling |
4 |
| Spatial Correlation and Value Prediction in Convolutional Neural Networks |
4 |
| RTSim: A Cycle-Accurate Simulator for Racetrack Memories |
4 |
| HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube |
4 |
| SMT-SA: Simultaneous Multithreading in Systolic Arrays |
3 |
| Counter Advance for Reliable Encryption in Phase Change Memory |
3 |
| Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications |
3 |
| RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware |
3 |
| TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering |
3 |
| Sensing CPU Voltage Noise Through Electromagnetic Emanations |
3 |
| A Scalable HW-Based Inline Deduplication for SSD Arrays |
3 |
| Regression Prefetcher with Preprocessing for DRAM-PCM Hybrid Main Memory |
3 |
| Orbital Edge Computing: Machine Inference in Space |
3 |
| EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs |
2 |
| Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions |
2 |
| Coordinated DVFS and Precision Control for Deep Neural Networks |
2 |
| AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs |
2 |
| TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches |
2 |
| CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection |
2 |
| Design of Generalized Pipeline Cellular Array in Quantum-Dot Cellular Automata |
2 |
| Accelerator for Sparse Machine Learning |
1 |
| Birkhoff-Von Neumann Switch Based on Greedy Scheduling |
1 |
| Enabling Massive Multi-Threading with Fast Hashing |
1 |
| Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance |
1 |
| A New Class of Covert Channels Exploiting Power Management Vulnerabilities |
1 |
| Asymmetric Resilience for Accelerator-Rich Systems |
1 |
| Amoeba: An Autonomous Backup and Recovery SSD for Ransomware Attack Defense |
1 |
| Flow-Based Simulation Methodology |
1 |
| Precise Runahead Execution |
1 |
| The EH Model: Analytical Exploration of Energy-Harvesting Architectures |
1 |
| MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem |
1 |
| SSD Performance Modeling Using Bottleneck Analysis |
1 |
| Nile: A Programmable Monitoring Coprocessor |
1 |
| Detect DRAM Disturbance Error by Using Disturbance Bin Counters |
1 |
| Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning |
1 |
| KSM: Online Application-Level Performance Slowdown Prediction for Spatial Multitasking GPGPU |
1 |
| LEO: Low Overhead Encryption ORAM for Non-Volatile Memories |
1 |
| TERMinator Suite: Benchmarking Privacy-Preserving Architectures |
1 |
| Zebra Refresh: Value Transformation for Zero-Aware DRAM Refresh Reduction |
1 |
| On Memory System Design for Stochastic Computing |
1 |
| An Alternative Analytical Approach to Associative Processing |
1 |
| ARSENAL: Architecture for Secure Non-Volatile Memories |
1 |
| Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation |
1 |
| PIMSim: A Flexible and Detailed Processing-in-Memory Simulator |
1 |
| Performance and Fairness Improvement on CMPs Considering Bandwidth and Cache Utilization |
1 |
