| FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability |
21 |
| Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures |
19 |
| Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K |
14 |
| Cryogenic Temperature Characterization of a 28-nm FD-SOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration |
11 |
| Hysteresis Reduction in Negative Capacitance Ge PFETs Enabled by Modulating Ferroelectric Properties in HfZrOx |
11 |
| Tunneling Transistors Based on MoS2/MoTe2 Van der Waals Heterostructures |
11 |
| Direct Correlation of Ferroelectric Properties and Memory Characteristics in Ferroelectric Tunnel Junctions |
10 |
| Ferroelectric HfO2 Tunnel Junction Memory With High TER and Multi-Level Operation Featuring Metal Replacement Process |
10 |
| Development and Fabrication of AlGaInP-Based Flip-Chip Micro-LEDs |
10 |
| Experimental Investigations of State-of-the-Art 650-V Class Power MOSFETs for Cryogenic Power Conversion at 77K |
10 |
| Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si-0. Ge-0. Ge Gate-All-Around NSFET for 5nm Technology Node |
9 |
| Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part I: Al/Mo/Pr0.7Ca0.3MnO3 Material Improvements and Device Measurements |
9 |
| High-Performance Normally Off p-GaN Gate HEMT With Composite AlN/Al0.17Ga0.83N/Al0.3Ga0.7N Barrier Layers Design |
9 |
| Integrated Active-Matrix Capacitive Sensor Using a-IGZO TFTs for AMOLED |
9 |
| Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs |
9 |
| Lateral beta-Ga2O3 Schottky Barrier Diode on Sapphire Substrate With Reverse Blocking Voltage of 1.7 kV |
9 |
| A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors |
8 |
| Comprehensive Analysis and Optimal Design of Ge/GeSn/Ge p-n-p Infrared Heterojunction Phototransistors |
8 |
| Dynamic Control of AlGaN/GaN HEMT Characteristics by Implementation of a p-GaN Body-Diode-Based Back-Gate |
8 |
| High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave Operation |
7 |
| Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate |
7 |
| Design of Power- and Variability-Aware Nonvolatile RRAM Cell Using Memristor as a Memory Element |
7 |
| 3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV) |
7 |
| Multi-V-th Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing |
7 |
| Analysis and Simulation of Low-Frequency Noise in Indium-Zinc-Oxide Thin-Film Transistors |
7 |
| Hot-Carrier Degradation in Power LDMOS: Selective LOCOS- Versus STI-Based Architecture |
7 |
| Operation Up to 500 degrees C of Al0.85Ga0.15N/Al0.7Ga0.3N High Electron Mobility Transistors |
7 |
| Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations |
7 |
| A High Performance Operational Amplifier Using Coplanar Dual Gate a-IGZO TFTs |
6 |
| Spin Splitter Based on Magnetically Confined Semiconductor Microstructure Modulated by Spin-Orbit Coupling |
6 |
| Barrier Inhomogeneity of Schottky Diode on Nonpolar AlN Grown by Physical Vapor Transport |
6 |
| High-Gain Transimpedance Amplifier for Flexible Radiation Dosimetry Using InGaZnO TFTs |
6 |
| On the Physical Mechanism of Transient Negative Capacitance Effect in Deep Subthreshold Region |
6 |
| Impact of the Stacking Order of HfOX and AlOX Dielectric Films on RRAM Switching Mechanisms to Behave Digital Resistive Switching and Synaptic Characteristics |
6 |
| On the Characterization and Separation of Trapping and Ferroelectric Behavior in HfZrO FET |
6 |
| The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS |
6 |
| A Physical Model for the Hysteresis in MoS2 Transistors |
6 |
| Thickness Effect on Operational Modes of ZnGa2O4 MOSFETs |
6 |
| 2-Bit/Cell Operation of Hf0.5Zr0.5O2 Based FeFET Memory Devices for NAND Applications |
6 |
| Fabrication and Study on Red Light Micro-LED Displays |
6 |
| Normally-OFF GaN MIS-HEMT With F- Doped Gate Insulator Using Standard Ion Implantation |
6 |
| SCR-Based ESD Protection Using a Penta-Well for 5 V Applications |
6 |
| Improved Uniformity and Endurance Through Suppression of Filament Overgrowth in Electrochemical Metallization Memory With AgInSbTe Buffer Layer |
6 |
| A Method to Reduce Forming Voltage Without Degrading Device Performance in Hafnium Oxide-Based 1T1R Resistive Random Access Memory |
5 |
| Experimental Observation and Simulation Model for Transient Characteristics of Negative-Capacitance in Ferroelectric HfZrO2 Capacitor |
5 |
| Ferroelectric HfZrOx FETs on SOI Substrate With Reverse-DIBL (Drain-Induced Barrier Lowering) and NDR (Negative Differential Resistance) |
5 |
| Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs |
5 |
| A Graphene Oxide Quantum Dots Embedded Charge Trapping Memory With Enhanced Memory Window and Data Retention |
5 |
| Evaluation of Si:HfO2 Ferroelectric Properties in MFM and MFIS Structures |
5 |
| Interface Coupled Photodetector (ICPD) With High Photoresponsivity Based on Silicon-on-Insulator Substrate (SOI) |
5 |
