| Machine Learning for Hardware Security: Opportunities and Risks |
10 |
| Security Analysis of the Efficient Chaos Pseudo-random Number Generator Applied to Video Encryption |
6 |
| Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits |
5 |
| Test and Reliability in Approximate Computing |
5 |
| An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays |
4 |
| Impact of Aging on the Reliability of Delay PUFs |
3 |
| Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing |
3 |
| Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions |
3 |
| A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip |
3 |
| The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata |
3 |
| Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library |
3 |
| Activity Factor Based Hardware Trojan Detection and Localization |
2 |
| Testing Signals for Electronics: Criteria for Synthesis |
2 |
| Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection |
2 |
| Saleh Model and Digital Predistortion for Power Amplifiers in Wireless Communications Using the Third-Order Intercept Point |
2 |
| Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag |
2 |
| Reliability Testing of 3D-Printed Electromechanical Scanning Devices |
2 |
| An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator |
2 |
| Exploiting Multi-Phase On-Chip Voltage Regulators as Strong PUF Primitives for Securing IoT |
2 |
| Security Analysis and Improvement of the Pseudo-random Number Generator Based on Piecewise Logistic Map |
2 |
| An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM |
2 |
| Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects |
2 |
| An Integrated on-Silicon Verification Method for FPGA Overlays |
2 |
| Multi-Step-Ahead Prediction for a CMOS Low Noise Amplifier Aging Due to NBTI and HCI Using Neural Networks |
2 |
| Automation of Test Program Synthesis for Processor Post-silicon Validation |
1 |
| Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC |
1 |
| NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach |
1 |
| Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints |
1 |
| Low-Cost Strategy for Bus Propagation Delay Reduction |
1 |
| Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations |
1 |
| Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110MHz) |
1 |
| Testing of Current Carrying Capacity of Conducting Tracks in High Power Flexible Printed Circuit Boards |
1 |
| Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements |
1 |
| An Integrated Framework for Application Independent Testing of FPGA Interconnect |
1 |
| Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories |
1 |
| Logic Locking: A Survey of Proposed Methods and Evaluation Metrics |
1 |
| High Performance Static Segment On-Chip Memory for Image Processing Applications |
1 |
| Generation Methodology for Good-Enough Approximate Modules of ATMR |
1 |
| LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs |
1 |
| Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness |
1 |
| RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing |
1 |
| Golden-Free Processor Hardware Trojan Detection Using Bit Power Consistency Analysis |
1 |
| A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters |
1 |
| Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning |
1 |
| Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing |
1 |
| Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs |
1 |
| Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization |
1 |
| Measurement of Nonlinear Dielectric Behaviour of Semiconductor Material Under Microwave Field in Dual-Mode Rectangular Cavity |
1 |
| Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies |
1 |
| Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test |
1 |
